Job summary
A technology company is seeking an Expert Logic Design Engineer to lead the architecture, design, and optimization of advanced FPGA and ASIC control platforms. The role involves solving complex digital design challenges related to timing, latency, and performance, working closely with cross-disciplinary engineering teams to develop proprietary digital intellectual property for innovative hardware platforms used in cutting-edge quantum computing systems.
Location and work setup
- Location
- Oslo
- Work setup
- Remote
Responsibilities
Lead architecture and RTL implementation of complex, high-performance FPGA and ASIC digital subsystems. Design and optimize configurable, ultra-low-latency digital logic using SystemVerilog. Oversee the end-to-end development of digital IP from requirements through integration, making architectural decisions to improve timing, latency, resource efficiency, scalability, and power consumption. Address challenging timing closure and synchronization issues, develop advanced digital processing and control architectures, and define hardware-software interfaces. Collaborate with verification engineers to establish testing strategies and ensure functional coverage. Review designs to identify risks and provide technical guidance. Contribute to platform evolution and reusable IP development. Promote engineering best practices and design quality throughout the development lifecycle.
Qualifications
Bachelor's or Master's degree in Electrical or Computer Engineering or equivalent experience. Over 6 years of experience in complex FPGA or ASIC digital logic design. Expert proficiency in SystemVerilog RTL design. Strong background in digital architecture and microarchitecture design. Proven ability to independently deliver complex digital IP. Deep understanding of RTL optimization, logic synthesis, static timing analysis, and timing closure processes. Experience with deterministic latency optimization, high-frequency clock design, resource management, and power efficiency. Knowledge of synchronous design, clock-domain crossing, clocking architectures, and hardware interfaces. Familiarity with FPGA and ASIC methodologies and simulation-based verification tools. Excellent analytical, leadership, and communication skills. Fluency in English for international collaboration.