Job summary
An experienced engineer is sought to design and optimize high-performance digital logic for FPGA and ASIC platforms, playing a key role in developing control systems tailored for advanced computing technologies. The position involves collaboration with a diverse international team to tackle complex hardware design challenges.
Location and work setup
- Location
- Oslo
- Work setup
- Remote
Responsibilities
Design and implement configurable, low-latency RTL modules using SystemVerilog. Develop digital logic for FPGA and ASIC applications focusing on signal processing and real-time control. Manage the full RTL lifecycle from architecture definition to verification. Optimize designs for timing, latency, power, and resource use. Perform synthesis and timing analysis to meet strict constraints. Collaborate with verification engineers for functional correctness and test coverage. Analyze system and software requirements to define hardware-software interfaces. Integrate proprietary digital intellectual property into complex designs. Participate in design reviews, debugging efforts, and continuous process improvements.
Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related fields, or equivalent experience. At least 4 years of professional experience in FPGA or ASIC digital logic design with hands-on RTL development using SystemVerilog. Solid understanding of digital logic design principles, computer architecture, and RTL microarchitecture. Experience with logic synthesis, static timing analysis, and design optimization. Knowledge of clock-domain crossing, synchronous digital design, and hardware interfaces. Experience with simulation-driven verification and debugging. Strong analytical, problem-solving, and communication skills, including proficiency in English for international collaboration.